Project 1789/INCITS 413 - Information technology - RapidIOTM Interconnect Specification (version 1.3)


Introduction from Draft:

The RapidIO™ architecture was developed to address the need for a high-performance low pin count packet-switched system level
interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and
high performance embedded applications. It is intended primarily as an intra-system interconnect, allowing chip-to-chip and boardto-
board communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth,
low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message
passing, and software managed programming models. In its simplest form, the interface can be implemented in a FPGA end point.
The interconnect defines a protocol independent of a physical implementation. The physical features of an implementation utilizing
the interconnect are defined by the requirements of the implementation, such as I/O signaling levels, interconnect topology, physical
layer protocol, error detection, and so forth. The architecture is intended and partitioned to allow adaptation to a multitude of applications.

Scope from Project Proposal:

RapidIO™ is a definition of a system interconnect. System concepts such as processor programming models, memory coherency models and caching are beyond the scope of the RapidIO™ architecture. The support of memory coherency models, through caches, memory directories (or equivalent, to hold state and speed up remote memory access) is the responsibility of the end points (processors, memory, and possibly I/O devices), using RapidIO™ operations. RapidIO™ provides the operations to construct a wide variety of systems, based on programming models that range from strong consistency through total store ordering to weak ordering. Inter-operability between end points supporting different coherency/caching/directory models is not guaranteed. However, groups of end-points with conforming models can be linked to others conforming to different models on the same RapidIO™ fabric. These different groups can communicate through RapidIO™ messaging or I/O operations.